The present invention relates to semiconductor devices, and more particularly to semiconductor devices having a fin structure and a method of manufacturing the same.
As the size of semiconductor devices is steadily scaled down, the performance of semiconductor devices is continuously improved. From a structural point of view, single-gate transistors have been replaced by multi-gate transistors. Fin field-effect transistors (FinFETs) are widely used in integrated circuits for their increased gate widths over planar transistors.
FIG. 1 is a perspective view of a fin field effect transistor (FinFET). As shown in FIG. 1 for illustrative purposes, the FinFET includes a semiconductor substrate 10′, a fin structure (alternatively referred to as “fin”) 14′ disposed on substrate 10′, a dielectric layer 11′ covering substrate 10′ and a portion of side surfaces of fin structure 14′, and a gate structure disposed across fin structure 14′. The gate structure includes a gate electrode 12′ and spacers 13′ disposed on opposite sides of gate electrode 12′.
Similar to a planar transistor, the source/drain regions in fin structure 14′ may be formed adjacent the gate electrode. However, since the fin structure of the FinFET is typically narrow, current crowding may occur. In addition, it is difficult to place contact plugs onto the source/drain regions of the fin structure. Epitaxial layers are thus formed on the fin structure to increase the volume of the fin structure using epitaxial growth processes.
Epitaxial growth processes have drawbacks. FIG. 2 is a cross-sectional view of an epitaxial layer grown from the semiconductor fin along the vertical direction of the line A-A′ of FIG. 1. Referring to FIG. 2, an epitaxial layer 22′ is grown on the source and drain regions in the fin structure 14′. Compared with a conventional planar transistor, the volumes of source/drain regions are not confined by shallow trench isolation (STI) and can be adjusted according to semiconductor device design requirements. However, because epitaxial layer 22′ is typically formed of pure silicon, and the growth rate of the epitaxial layer is smaller on the (111) crystal plane than on other crystal planes, epitaxial layer 22′ may extend laterally and form multiple facets 8′ having substantially a rectangular profile or shape, whose corners reduce the air gap (lateral distance) between epitaxial layers grown from adjacent fins structures. Further, since the lateral distance between the grown epitaxial layers of adjacent fin structures can be reduced excessively, voids 30′ will be undesirably formed when the laterally growing epitaxial layers of adjacent fin structures 14′ merge together, as shown in FIG. 3.